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[/] [aemb/] [branches/] [AEMB2_712/] [sim/] [cversim] - Rev 49

Rev	Log message	Author	Age	Path
49	Added random seed for simulation.	sybreon	6220d 23h	/aemb/branches/AEMB2_712/sim/cversim
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6427d 14h	/aemb/branches/AEMB2_712/sim/cversim
2	initial import	sybreon	6461d 16h	/aemb/branches/AEMB2_712/sim/cversim