URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_core.v] - Rev 196

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5634d 03h	/aemb/trunk/rtl/verilog/aeMB_core.v
71	Old version deprecated.	sybreon	6106d 07h	/aemb/trunk/rtl/verilog/aeMB_core.v
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6138d 02h	/aemb/trunk/rtl/verilog/aeMB_core.v
38	Added interrupt support.	sybreon	6283d 03h	/aemb/trunk/rtl/verilog/aeMB_core.v
36	Removed asynchronous reset signal.	sybreon	6296d 12h	/aemb/trunk/rtl/verilog/aeMB_core.v
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6316d 21h	/aemb/trunk/rtl/verilog/aeMB_core.v
22	Added support for 8-bit and 16-bit data types.	sybreon	6317d 23h	/aemb/trunk/rtl/verilog/aeMB_core.v
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6332d 17h	/aemb/trunk/rtl/verilog/aeMB_core.v
11	Removed unused signals	sybreon	6339d 15h	/aemb/trunk/rtl/verilog/aeMB_core.v
3	initial import	sybreon	6365d 04h	/aemb/trunk/rtl/verilog/aeMB_core.v