URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_ctrl.v] - Rev 191

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5727d 13h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
72	Minor code cleanup.	sybreon	6192d 15h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
65	Fixed minor typo causing synthesis failure.	sybreon	6207d 23h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
62	Fixed minor typo.	sybreon	6208d 09h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6208d 10h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6212d 15h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
53	Added GET/PUT support through a FSL bus.	sybreon	6213d 11h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
51	Fixed data WISHBONE arbitration problem (reported by J Lee).	sybreon	6214d 14h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
50	Parameterised optional components.	sybreon	6214d 18h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6220d 13h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6221d 05h	/aemb/trunk/rtl/verilog/aeMB_ctrl.v