URL https://opencores.org/ocsvn/aemb/aemb/trunk

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[/] [aemb/] [trunk/] [rtl/] [verilog/] [aeMB_ibuf.v] - Rev 202

Rev	Log message	Author	Age	Path
191	New directory structure.	root	5729d 02h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
105	Patch interrupt bug.	sybreon	6142d 20h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
103	Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)	sybreon	6144d 05h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
96	Stalls pipeline on MUL/BSF instructions results in minor speed improvements.	sybreon	6168d 22h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
70	Change interrupt to positive level triggered interrupts.	sybreon	6202d 05h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
63	Fixed interrupt signal synchronisation.	sybreon	6209d 21h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
61	Changed interrupt handling system (reported by M. Ettus).	sybreon	6209d 22h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
55	Upgraded license to LGPLv3. Significant performance optimisations.	sybreon	6214d 04h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
45	Minor code cleanup.	sybreon	6221d 12h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
44	Added better (beta) interrupt support. Changed MSR_IE to disabled at reset as per MB docs.	sybreon	6222d 01h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6222d 17h	/aemb/trunk/rtl/verilog/aeMB_ibuf.v