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[/] [aemb/] [trunk/] [rtl/] [verilog] - Rev 149

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Rev Log message Author Age Path
149 Minor performance optimisation. sybreon 5950d 03h /aemb/trunk/rtl/verilog
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 5950d 08h /aemb/trunk/rtl/verilog
147 Disconnect from pipeline. sybreon 5950d 11h /aemb/trunk/rtl/verilog
140 Fixed minor typos. sybreon 5950d 11h /aemb/trunk/rtl/verilog
134 Minor performance improvements. sybreon 5951d 10h /aemb/trunk/rtl/verilog
132 Fixed minor typos. sybreon 5952d 02h /aemb/trunk/rtl/verilog
131 Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor. sybreon 5952d 02h /aemb/trunk/rtl/verilog
127 Fixed pipelined latching of data bug. sybreon 5954d 13h /aemb/trunk/rtl/verilog
126 Fixed CMP bug. sybreon 5954d 13h /aemb/trunk/rtl/verilog
125 Passes arithmetic tests with single thread. sybreon 5956d 15h /aemb/trunk/rtl/verilog
124 FASM removed. sybreon 5956d 15h /aemb/trunk/rtl/verilog
120 Basic version with some features left out. sybreon 5957d 11h /aemb/trunk/rtl/verilog
119 Initial import. sybreon 5957d 11h /aemb/trunk/rtl/verilog
118 Initial import. sybreon 5960d 03h /aemb/trunk/rtl/verilog
114 changed MSR bits sybreon 5966d 12h /aemb/trunk/rtl/verilog
105 Patch interrupt bug. sybreon 6048d 03h /aemb/trunk/rtl/verilog
103 Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus) sybreon 6049d 12h /aemb/trunk/rtl/verilog
102 Fix MTS during interrupt vectoring bug (reported by M. Ettus). sybreon 6049d 12h /aemb/trunk/rtl/verilog
101 Made multiplier pause with pipeline sybreon 6059d 08h /aemb/trunk/rtl/verilog
100 multiplier issues sybreon 6059d 08h /aemb/trunk/rtl/verilog

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