URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl] - Rev 132

Rev	Log message	Author	Age	Path
132	Fixed minor typos.	sybreon	5951d 17h	/aemb/trunk/rtl
131	Passes basic tests. Minor documentation changes to make it compatible with iverilog pre-processor.	sybreon	5951d 17h	/aemb/trunk/rtl
127	Fixed pipelined latching of data bug.	sybreon	5954d 04h	/aemb/trunk/rtl
126	Fixed CMP bug.	sybreon	5954d 04h	/aemb/trunk/rtl
125	Passes arithmetic tests with single thread.	sybreon	5956d 06h	/aemb/trunk/rtl
124	FASM removed.	sybreon	5956d 06h	/aemb/trunk/rtl
120	Basic version with some features left out.	sybreon	5957d 02h	/aemb/trunk/rtl
119	Initial import.	sybreon	5957d 02h	/aemb/trunk/rtl
118	Initial import.	sybreon	5959d 18h	/aemb/trunk/rtl
114	changed MSR bits	sybreon	5966d 02h	/aemb/trunk/rtl
105	Patch interrupt bug.	sybreon	6047d 17h	/aemb/trunk/rtl
103	Patched problem where memory access followed by dual cycle instructions were not stalling correctly (submitted by M. Ettus)	sybreon	6049d 02h	/aemb/trunk/rtl
102	Fix MTS during interrupt vectoring bug (reported by M. Ettus).	sybreon	6049d 02h	/aemb/trunk/rtl
101	Made multiplier pause with pipeline	sybreon	6058d 23h	/aemb/trunk/rtl
100	multiplier issues	sybreon	6058d 23h	/aemb/trunk/rtl
99	Minor cleanup	sybreon	6070d 18h	/aemb/trunk/rtl
96	Stalls pipeline on MUL/BSF instructions results in minor speed improvements.	sybreon	6073d 20h	/aemb/trunk/rtl
95	Abstracted simulation kernel (aeMB_sim) to split simulation models from synthesis models.	sybreon	6075d 22h	/aemb/trunk/rtl
94	Prevent fHZD & rBRA[1]	sybreon	6077d 20h	/aemb/trunk/rtl
93	Minor enable fix	sybreon	6077d 20h	/aemb/trunk/rtl