URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl] - Rev 28

Rev	Log message	Author	Age	Path
28	Fixed simulation bug.	sybreon	6288d 00h	/aemb/trunk/rtl
27	Removed some unnecessary bubble control.	sybreon	6288d 11h	/aemb/trunk/rtl
26	Fixed minor synthesis bug.	sybreon	6288d 11h	/aemb/trunk/rtl
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6288d 15h	/aemb/trunk/rtl
24	Made minor performance optimisations.	sybreon	6289d 01h	/aemb/trunk/rtl
23	Fixed minor simulation bug.	sybreon	6289d 16h	/aemb/trunk/rtl
22	Added support for 8-bit and 16-bit data types.	sybreon	6289d 17h	/aemb/trunk/rtl
19	Added initial unified memory core.	sybreon	6302d 02h	/aemb/trunk/rtl
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6302d 19h	/aemb/trunk/rtl
17	Cosmetic changes	sybreon	6303d 23h	/aemb/trunk/rtl
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6304d 11h	/aemb/trunk/rtl
14	Added initial interrupt/exception support.	sybreon	6311d 01h	/aemb/trunk/rtl
11	Removed unused signals	sybreon	6311d 09h	/aemb/trunk/rtl
10	Fixed minor bugs	sybreon	6311d 09h	/aemb/trunk/rtl
9	Extended testbench code	sybreon	6311d 09h	/aemb/trunk/rtl
8	Fixed memory read-write data hazard	sybreon	6311d 09h	/aemb/trunk/rtl
7	Added CMP instruction	sybreon	6311d 09h	/aemb/trunk/rtl
5	Fixed endian correction issues on data bus.	sybreon	6312d 01h	/aemb/trunk/rtl
4	Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by Joon Lee.	sybreon	6320d 03h	/aemb/trunk/rtl
3	initial import	sybreon	6336d 21h	/aemb/trunk/rtl