URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl] - Rev 38

Rev	Log message	Author	Age	Path
38	Added interrupt support.	sybreon	6254d 20h	/aemb/trunk/rtl
36	Removed asynchronous reset signal.	sybreon	6268d 06h	/aemb/trunk/rtl
35	Added async BRA/DLY signals for future clock, reset, and interrupt features.	sybreon	6269d 02h	/aemb/trunk/rtl
34	Corrected speed issues after rev 1.9 update.	sybreon	6269d 16h	/aemb/trunk/rtl
33	Fixed minor data hazard bug spotted by Matt Ettus.	sybreon	6284d 23h	/aemb/trunk/rtl
31	Removed byte acrobatics.	sybreon	6284d 23h	/aemb/trunk/rtl
28	Fixed simulation bug.	sybreon	6287d 23h	/aemb/trunk/rtl
27	Removed some unnecessary bubble control.	sybreon	6288d 10h	/aemb/trunk/rtl
26	Fixed minor synthesis bug.	sybreon	6288d 10h	/aemb/trunk/rtl
25	Added code documentation. Improved size & speed of rtl/verilog/aeMB_aslu.v	sybreon	6288d 14h	/aemb/trunk/rtl
24	Made minor performance optimisations.	sybreon	6289d 00h	/aemb/trunk/rtl
23	Fixed minor simulation bug.	sybreon	6289d 16h	/aemb/trunk/rtl
22	Added support for 8-bit and 16-bit data types.	sybreon	6289d 16h	/aemb/trunk/rtl
19	Added initial unified memory core.	sybreon	6302d 02h	/aemb/trunk/rtl
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6302d 18h	/aemb/trunk/rtl
17	Cosmetic changes	sybreon	6303d 22h	/aemb/trunk/rtl
16	Added pipeline stalling from incomplete bus cycles. Separated sync and async portions of code.	sybreon	6304d 10h	/aemb/trunk/rtl
14	Added initial interrupt/exception support.	sybreon	6311d 01h	/aemb/trunk/rtl
11	Removed unused signals	sybreon	6311d 09h	/aemb/trunk/rtl
10	Fixed minor bugs	sybreon	6311d 09h	/aemb/trunk/rtl