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[/] [aemb/] [trunk/] [rtl] - Rev 44

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Rev Log message Author Age Path
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6127d 14h /aemb/trunk/rtl
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6128d 06h /aemb/trunk/rtl
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6138d 14h /aemb/trunk/rtl
38 Added interrupt support. sybreon 6283d 15h /aemb/trunk/rtl
36 Removed asynchronous reset signal. sybreon 6297d 00h /aemb/trunk/rtl
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6297d 21h /aemb/trunk/rtl
34 Corrected speed issues after rev 1.9 update. sybreon 6298d 11h /aemb/trunk/rtl
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6313d 17h /aemb/trunk/rtl
31 Removed byte acrobatics. sybreon 6313d 17h /aemb/trunk/rtl
28 Fixed simulation bug. sybreon 6316d 18h /aemb/trunk/rtl
27 Removed some unnecessary bubble control. sybreon 6317d 05h /aemb/trunk/rtl
26 Fixed minor synthesis bug. sybreon 6317d 05h /aemb/trunk/rtl
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6317d 09h /aemb/trunk/rtl
24 Made minor performance optimisations. sybreon 6317d 19h /aemb/trunk/rtl
23 Fixed minor simulation bug. sybreon 6318d 10h /aemb/trunk/rtl
22 Added support for 8-bit and 16-bit data types. sybreon 6318d 11h /aemb/trunk/rtl
19 Added initial unified memory core. sybreon 6330d 20h /aemb/trunk/rtl
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6331d 13h /aemb/trunk/rtl
17 Cosmetic changes sybreon 6332d 17h /aemb/trunk/rtl
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6333d 05h /aemb/trunk/rtl

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