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[/] [aemb/] [trunk/] [sim/] [verilog/] [edk32.v] - Rev 49

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Rev Log message Author Age Path
49 Added random seed for simulation. sybreon 6122d 11h /aemb/trunk/sim/verilog/edk32.v
43 Added interrupt simulation.
Changed "human readable" simulation output.
sybreon 6125d 03h /aemb/trunk/sim/verilog/edk32.v
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.
sybreon 6125d 19h /aemb/trunk/sim/verilog/edk32.v

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