URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [sim] - Rev 50

Rev	Log message	Author	Age	Path
50	Parameterised optional components.	sybreon	6156d 05h	/aemb/trunk/sim
49	Added random seed for simulation.	sybreon	6159d 09h	/aemb/trunk/sim
43	Added interrupt simulation. Changed "human readable" simulation output.	sybreon	6162d 00h	/aemb/trunk/sim
41	New EDK 3.2 compatible design with optional barrel-shifter and multiplier. Fixed various minor data hazard bugs. Code compatible with -O0/1/2/3/s generated code.	sybreon	6162d 16h	/aemb/trunk/sim
39	Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus.	sybreon	6173d 00h	/aemb/trunk/sim
38	Added interrupt support.	sybreon	6318d 01h	/aemb/trunk/sim
31	Removed byte acrobatics.	sybreon	6348d 04h	/aemb/trunk/sim
30	Minor updates as sw/c/aeMB_testbench.c got updated.	sybreon	6351d 04h	/aemb/trunk/sim
22	Added support for 8-bit and 16-bit data types.	sybreon	6352d 21h	/aemb/trunk/sim
19	Added initial unified memory core.	sybreon	6365d 06h	/aemb/trunk/sim
18	Moved testbench into /sim/verilog. Simulation cleanups.	sybreon	6365d 23h	/aemb/trunk/sim
15	Removed ROM file. Please generate it from the SW directory.	sybreon	6374d 05h	/aemb/trunk/sim
13	Fibonacci rom	sybreon	6374d 13h	/aemb/trunk/sim
2	initial import	sybreon	6400d 02h	/aemb/trunk/sim