URL https://opencores.org/ocsvn/aes_highthroughput_lowarea/aes_highthroughput_lowarea/trunk

Subversion Repositories aes_highthroughput_lowarea

[/] [aes_highthroughput_lowarea/] [trunk/] [verilog/] [rtl] - Rev 8

Rev	Log message	Author	Age	Path
8	Added core specification document, core top example module and FPGA synthesis project files.	motilito	4607d 09h	/aes_highthroughput_lowarea/trunk/verilog/rtl
7	Added AES KAT test bench and simulation batch files for Icarus Verilog. Note that reset polarity was changed to rising edge (posedge).	motilito	5062d 08h	/aes_highthroughput_lowarea/trunk/verilog/rtl
5	Updating sub-directory structure	motilito	5062d 12h	/aes_highthroughput_lowarea/trunk/verilog/rtl