URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [tests] - Rev 36

Rev	Log message	Author	Age	Path
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4796d 08h	/amber/trunk/hw/tests
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4797d 16h	/amber/trunk/hw/tests
20	Added feature to A25 core to directly use a read value from the write back stage to reduce the stall to 1 cycle when there is a register conflict with the following instruction. This increases performance by about 3%.	csantifort	4882d 15h	/amber/trunk/hw/tests
17	amber25 core bug fix. The return address for irq interrupts was off by 4 bytes when the interrupt occurred during a stm instruction with the following instruction having some register conflicts. Added test irq_stm to catch the bug. Cleaned up some header descriptions	csantifort	4886d 13h	/amber/trunk/hw/tests
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	4889d 04h	/amber/trunk/hw/tests
11	Added vmlinux test.	csantifort	4905d 16h	/amber/trunk/hw/tests
6	Set ignore property for output files	csantifort	4918d 13h	/amber/trunk/hw/tests
2	Baseline release of the Amber 2 core	csantifort	4919d 14h	/amber/trunk/hw/tests