| Rev |
Log message |
Author |
Age |
Path |
| 89 |
CHange registered outputs with non-zero initial values to wires with an internal register.
This works around an issue with Altera (Quartus) synthesis where any port registers are given an initial vale of zero. |
csantifort |
3502d 16h |
/amber/trunk/hw/vlog/amber23 |
| 88 |
Added the carry in fix added recently to the a23 core to a25 core. |
csantifort |
3502d 16h |
/amber/trunk/hw/vlog/amber23 |
| 87 |
Added support for "When an Operand2 constant is used with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[31] of the constant, if the constant is greater than 255 and can be produced by shifting an 8-bit value" to amber23 |
csantifort |
3502d 20h |
/amber/trunk/hw/vlog/amber23 |
| 84 |
Fixed some typos - no functional change |
csantifort |
3515d 23h |
/amber/trunk/hw/vlog/amber23 |
| 83 |
Fixed bug with carry bit - now only use the carry bit as an input to specific instruments that use it - add with carry and subtract with carry |
csantifort |
3516d 00h |
/amber/trunk/hw/vlog/amber23 |
| 82 |
Fixed overflag bug, ldmia user regs bug and status_bits_mode set on non-ececuting command bug |
csantifort |
3529d 12h |
/amber/trunk/hw/vlog/amber23 |
| 74 |
The patch implements barrel shifter using rotate as a main primitive.
The design was optimized for Altera Cyclone III FPGA and can be reused
with other FPGA vendors and products.
The patch integrates the FPGA-optimized barrel shifter into the
Amber 23 core when it is build for Altera FPGA.
The patch reduces footprint from 1178 to 339 LEs keeping Fmax at 57-60 MHz.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4215d 18h |
/amber/trunk/hw/vlog/amber23 |
| 73 |
The patch introduces a new configuration option `A23_RAM_REGISTER_BANK,
which controls instantiation of Amber 23 register bank.
If the option is set, a ram-based variant of the register bank is instantiated.
It can be useful in low-end FPGA designs, where flipflops and muxes are costly.
Altera Cyclone III resource utilization:
- flipflop-based register bank: 1583 combinationals + 856 registers
- ram-based register bank: 268 combinationals + 156 registers
Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4215d 18h |
/amber/trunk/hw/vlog/amber23 |
| 72 |
5 bit "OH_USR" constant was used when 2 bit "USR" should be used.
Both of the constants are 0.
The fault was introduced by ram-based register bank commit.
Contributed by: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4215d 18h |
/amber/trunk/hw/vlog/amber23 |
| 71 |
Original Amber 23 core uses asyncronous implementation of register bank.
It leads to some problems with ram-based implementation of the register bank,
because at least Altera FPGAs uses syncronous ram blocks, so the whole address
needs to be latched.
The patch exposes non-registered versions of register select signals to the
register bank, so the bank can build address and latch it in the syncronous
ram input register.
The patch is a pre-requisite for ram-based register bank implementation on Altera FPGA.
Contributed by Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no> |
csantifort |
4215d 18h |
/amber/trunk/hw/vlog/amber23 |
| 63 |
Add support for Xilinx ISim Verilog simulator.
Remove Virtex-6 files. |
csantifort |
4216d 00h |
/amber/trunk/hw/vlog/amber23 |
| 58 |
Use TB.clk_count for the decompiler messages and removed the local counter |
csantifort |
4790d 16h |
/amber/trunk/hw/vlog/amber23 |
| 54 |
Bug fix for bug reported by Botao Lee. The mode bits in the decode stage did not change immediately
after a mode switch from a teqp instruction, but 1 cycle later. This meant the wrong set of registers
was selected for writing to for 1 clock cycle. |
csantifort |
4807d 15h |
/amber/trunk/hw/vlog/amber23 |
| 53 |
Cleaned up Amber Verilog, removing unused signals. |
csantifort |
4822d 13h |
/amber/trunk/hw/vlog/amber23 |
| 43 |
Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test.
Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency. |
csantifort |
4895d 15h |
/amber/trunk/hw/vlog/amber23 |
| 42 |
Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete |
csantifort |
4913d 12h |
/amber/trunk/hw/vlog/amber23 |
| 15 |
Copied amber to amber23, Many system changes to support new amber25 core. |
csantifort |
5015d 08h |
/amber/trunk/hw/vlog/amber23 |
| 2 |
Baseline release of the Amber 2 core |
csantifort |
5045d 18h |
/amber/trunk/hw/vlog/amber |
