URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog] - Rev 15

Rev	Log message	Author	Age	Path
15	Copied amber to amber23, Many system changes to support new amber25 core.	csantifort	4862d 09h	/amber/trunk/hw/vlog
14	Re-wrote the behavioral clock generation code to more accurately calculate the sys_clk frequency. The previous version was not producing the correct frequency at higher frequenies due to rounding errors.	csantifort	4863d 21h	/amber/trunk/hw/vlog
13	Bug fix - added an extra state to the rx state machine to properly align reading the uart input to the middle of each bit.	csantifort	4863d 21h	/amber/trunk/hw/vlog
12	Added INITIALIZE_TO_ZERO parameter to keep instantiation idendical to generic sram models. The parameter is not used in the Xilinx models (they always init to zero) but it used in the generic models.	csantifort	4863d 21h	/amber/trunk/hw/vlog
11	Added vmlinux test.	csantifort	4878d 21h	/amber/trunk/hw/vlog
10	Removed parameters for unused peruipheral modules	csantifort	4880d 00h	/amber/trunk/hw/vlog
9	Change the format of mcr and mrc listings so they exactly match the dissasembly produced by the gnu tools. Write ip instead of r12 in listings.	csantifort	4880d 01h	/amber/trunk/hw/vlog
8	Change the value in the ID register to be compatible with the Linux code that parses it and picks a processor type.	csantifort	4880d 01h	/amber/trunk/hw/vlog
7	Added instructions to use Veritak simulator. Removed some unused functions from memory_configuration.v.	csantifort	4888d 15h	/amber/trunk/hw/vlog
2	Baseline release of the Amber 2 core	csantifort	4892d 19h	/amber/trunk/hw/vlog