URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [axi4-stream-bfm-master.vhdl] - Rev 17

Rev	Log message	Author	Age	Path
17	Added more pipelining, enhancements. Tested on BeMicro kit.	daniel.kho	3801d 04h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
16	Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input.	daniel.kho	3904d 00h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	3914d 21h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	3915d 01h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
11	Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match.	daniel.kho	3926d 00h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
9	Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages.	daniel.kho	3932d 20h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl