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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [axi4-stream-bfm-master.vhdl] - Rev 42

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42 Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files. daniel.kho 3697d 22h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3786d 01h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3888d 21h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3899d 18h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3899d 23h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3910d 21h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3917d 17h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis/axi4-stream-bfm-master.vhdl

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