URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [user.vhdl] - Rev 42

Rev	Log message	Author	Age	Path
42	Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files.	daniel.kho	3767d 13h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
17	Added more pipelining, enhancements. Tested on BeMicro kit.	daniel.kho	3855d 16h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
16	Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input.	daniel.kho	3958d 12h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
15	[minor]: cleaned up sources.	daniel.kho	3960d 19h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
14	Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap.	daniel.kho	3969d 09h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
13	Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well.	daniel.kho	3969d 14h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
11	Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match.	daniel.kho	3980d 12h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl
9	Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages.	daniel.kho	3987d 09h	/axi4_tlm_bfm/trunk/rtl/quartus-synthesis/user.vhdl