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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis] - Rev 18

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18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3852d 07h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3852d 07h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3955d 04h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
15 [minor]: cleaned up sources. daniel.kho 3957d 10h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3966d 01h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3966d 05h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3975d 09h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3977d 04h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3984d 00h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis

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