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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis] - Rev 44

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44 Committed latest changes to Quartus synthesis folder and some minor changes. daniel.kho 3380d 02h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
42 Major enhancements and bugfix. Used DDR for AXI BFM for enhanced functionality and performance. Tested in simulation; TODO update synthesis design files. daniel.kho 3725d 02h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
25 Refactored folders. daniel.kho 3802d 09h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
23 Added top-level user example used in technical paper. daniel.kho 3810d 03h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3813d 05h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3813d 05h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3916d 01h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
15 [minor]: cleaned up sources. daniel.kho 3918d 08h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3926d 22h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3927d 03h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3936d 07h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3938d 02h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3944d 22h /axi4_tlm_bfm/trunk/rtl/quartus-synthesis

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