URL https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk

Subversion Repositories axi4_tlm_bfm

[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [user.vhdl] - Rev 7

Rev	Log message	Author	Age	Path
7	[minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors).	daniel.kho	4057d 22h	/axi4_tlm_bfm/trunk/rtl/user.vhdl
6	[minor]: expanded some waveforms and show random stimulus from simulation script.	daniel.kho	4058d 03h	/axi4_tlm_bfm/trunk/rtl/user.vhdl
5	[minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'.	daniel.kho	4058d 07h	/axi4_tlm_bfm/trunk/rtl/user.vhdl
3	Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow.	daniel.kho	4059d 02h	/axi4_tlm_bfm/trunk/rtl/user.vhdl
2	Initial commit. Added packages and usage example for AXI4-Stream protocol. Added simulation scripts for ModelSim/QuestaSim.	daniel.kho	4059d 12h	/axi4_tlm_bfm/trunk/rtl/user.vhdl