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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [user.vhdl] - Rev 9

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9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3932d 14h /axi4_tlm_bfm/trunk/rtl/user.vhdl
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4032d 20h /axi4_tlm_bfm/trunk/rtl/user.vhdl
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4036d 14h /axi4_tlm_bfm/trunk/rtl/user.vhdl
6 [minor]: expanded some waveforms and show random stimulus from simulation script. daniel.kho 4036d 19h /axi4_tlm_bfm/trunk/rtl/user.vhdl
5 [minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. daniel.kho 4036d 23h /axi4_tlm_bfm/trunk/rtl/user.vhdl
3 Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. daniel.kho 4037d 18h /axi4_tlm_bfm/trunk/rtl/user.vhdl
2 Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim.		 daniel.kho 4038d 04h /axi4_tlm_bfm/trunk/rtl/user.vhdl

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