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[/] [axi4_tlm_bfm/] [trunk] - Rev 27

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27 Updated simulation scripts. daniel.kho 3844d 16h /axi4_tlm_bfm/trunk
26 Refactored simulation folders. daniel.kho 3844d 16h /axi4_tlm_bfm/trunk
25 Refactored folders. daniel.kho 3844d 17h /axi4_tlm_bfm/trunk
24 Updated simulation sources to reflect changes made for synthesis. daniel.kho 3844d 17h /axi4_tlm_bfm/trunk
23 Added top-level user example used in technical paper. daniel.kho 3852d 11h /axi4_tlm_bfm/trunk
22 Added pin assignments for BeMicro kit. Added demo top-level used in technical paper. daniel.kho 3852d 11h /axi4_tlm_bfm/trunk
21 Added synthesis files for Vivado. The RTL have not yet been updated with the latest changes available in the Quartus version. daniel.kho 3855d 13h /axi4_tlm_bfm/trunk
20 Updated simulation scripts. daniel.kho 3855d 13h /axi4_tlm_bfm/trunk
19 Updated synthesis constraints and scripts. daniel.kho 3855d 13h /axi4_tlm_bfm/trunk
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3855d 13h /axi4_tlm_bfm/trunk
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3855d 13h /axi4_tlm_bfm/trunk
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 3958d 10h /axi4_tlm_bfm/trunk
15 [minor]: cleaned up sources. daniel.kho 3960d 16h /axi4_tlm_bfm/trunk
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 3969d 07h /axi4_tlm_bfm/trunk
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 3969d 11h /axi4_tlm_bfm/trunk
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 3978d 15h /axi4_tlm_bfm/trunk
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 3980d 10h /axi4_tlm_bfm/trunk
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 3984d 10h /axi4_tlm_bfm/trunk
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 3987d 06h /axi4_tlm_bfm/trunk
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4087d 12h /axi4_tlm_bfm/trunk

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