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[/] [axi4_tlm_bfm] - Rev 20

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20 Updated simulation scripts. daniel.kho 3950d 05h /axi4_tlm_bfm
19 Updated synthesis constraints and scripts. daniel.kho 3950d 05h /axi4_tlm_bfm
18 Added hardware PRBS generator, modularised top-level by having separate file as the tester. daniel.kho 3950d 05h /axi4_tlm_bfm
17 Added more pipelining, enhancements. Tested on BeMicro kit. daniel.kho 3950d 06h /axi4_tlm_bfm
16 Moved transaction counter from BFM to user. This gives the user more control over the number of transactions. The BFM now treats this as an input. daniel.kho 4053d 02h /axi4_tlm_bfm
15 [minor]: cleaned up sources. daniel.kho 4055d 08h /axi4_tlm_bfm
14 Added simple reset logic and verified on hardware. Added PLL to supply test clock to SignalTap. daniel.kho 4063d 23h /axi4_tlm_bfm
13 Fixed one-cycle extra read issue, occurring during fast read. Verified on hardware as well. daniel.kho 4064d 03h /axi4_tlm_bfm
12 Used generic package instead of using tauhop.tlm (abstract package) directly, and updated corresponding context paths. Simulated fine with ModelSim 10.1b. [previous]: Previous update included synthesis fixes ported from simulation sources. daniel.kho 4073d 08h /axi4_tlm_bfm
11 Synthesised design with bugfixes discovered during simulation. Basically, these bugfixes just checks the design's behaviour against the AXI spec, and make sure the assumptions match. daniel.kho 4075d 02h /axi4_tlm_bfm
10 Written a few more directed testcases (in user.vhdl), and fixed several bugs. TODO move the testcases to the stimuli folder. daniel.kho 4079d 02h /axi4_tlm_bfm
9 Added synthesis files. Design debugged and synthesised with Quartus. Added synthesis script, and included OS-VVM simulation packages. daniel.kho 4081d 22h /axi4_tlm_bfm
8 [minor]: removed writeStream(). The write() procedure can be used for both stream and non-stream interfaces. For stream interfaces, just map the address argument to don't-cares. Made several other minor enhancements, simplifications. daniel.kho 4182d 04h /axi4_tlm_bfm
7 [minor]: renamed axi4-stream-bfm.vhdl to axi4-stream-bfm-master.vhdl so as to allow a future implementation of the AXI4-Stream slave / receiver. Changed simulation script to start GUI simulation only when there are no errors (previously, it brings up the GUI even when there are compilation errors). daniel.kho 4185d 22h /axi4_tlm_bfm
6 [minor]: expanded some waveforms and show random stimulus from simulation script. daniel.kho 4186d 03h /axi4_tlm_bfm
5 [minor]: refactored type names to use the convention 't_*' for more clarity. AXI4-Stream signal names also starts with a 't'. daniel.kho 4186d 07h /axi4_tlm_bfm
4 [minor]: Removed unused libraries from simulation script. daniel.kho 4187d 01h /axi4_tlm_bfm
3 Updated user.vhdl to use math_real's uniform for testbench randomisation. This is to avoid having to include third-party libraries into the project. Simulation of user.vhdl works - writeStream() procedure is used to send AXI4-Stream bus writes. More verification will follow. daniel.kho 4187d 02h /axi4_tlm_bfm
2 Initial commit.
Added packages and usage example for AXI4-Stream protocol.
Added simulation scripts for ModelSim/QuestaSim.		 daniel.kho 4187d 12h /axi4_tlm_bfm
1 The project and the structure was created root 4187d 23h /axi4_tlm_bfm

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