URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [sim] - Rev 18

Rev	Log message	Author	Age	Path
18	Added support for Xilinx Chips. Added support for AXI4-Lite bus. Can be used as an XPS IP.	ash_riple	4238d 10h	/bustap-jtag/trunk/sim
15	Released version 2.2.	ash_riple	4506d 13h	/bustap-jtag/trunk/sim
14	Changed dec to hex value of triggerPnum.	ash_riple	4507d 04h	/bustap-jtag/trunk/sim
13	Added minor syntax changes and Linux environment simulation script.	ash_riple	4507d 10h	/bustap-jtag/trunk/sim
12	Added timing information to the capture content.	ash_riple	4507d 17h	/bustap-jtag/trunk/sim
11	Added pre-trigger capture.	ash_riple	4508d 09h	/bustap-jtag/trunk/sim
10	Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure.	ash_riple	4513d 14h	/bustap-jtag/trunk/sim
9	Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do". Virtual JTAG stimulus can only be entered statically before simulation starts. FIFO operation can be simulated dynamically while simulation is run.	ash_riple	4514d 09h	/bustap-jtag/trunk/sim
2	Checked in working code base.	ash_riple	4526d 09h	/bustap-jtag/trunk/sim