OpenCores
URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag] - Rev 24

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 Added support for Qsys based avalon transaction monitoring. ash_riple 3580d 18h /bustap-jtag
23 Updated Altera Tcl script to 32bit address bus. ash_riple 3787d 17h /bustap-jtag
22 ash_riple 3787d 22h /bustap-jtag
21 ash_riple 3787d 23h /bustap-jtag
20 Added support for 32bit Address bus. ash_riple 3787d 23h /bustap-jtag
19 Minor changes. ash_riple 4201d 18h /bustap-jtag
18 Added support for Xilinx Chips.
Added support for AXI4-Lite bus. Can be used as an XPS IP.		 ash_riple 4201d 18h /bustap-jtag
17 Added unreachable trigger condition "@WR & @RD" checking. ash_riple 4447d 21h /bustap-jtag
16 Released version 2.2. ash_riple 4469d 22h /bustap-jtag
15 Released version 2.2. ash_riple 4469d 22h /bustap-jtag
14 Changed dec to hex value of triggerPnum. ash_riple 4470d 13h /bustap-jtag
13 Added minor syntax changes and Linux environment simulation script. ash_riple 4470d 18h /bustap-jtag
12 Added timing information to the capture content. ash_riple 4471d 02h /bustap-jtag
11 Added pre-trigger capture. ash_riple 4471d 17h /bustap-jtag
10 Changed the location/reference/generation of compiler directive file: jtag_sim_define.h, to have better code structure. ash_riple 4476d 22h /bustap-jtag
9 Added testbench with interactive GUI. Start it from "sim.bat" or "do sim.do".
Virtual JTAG stimulus can only be entered statically before simulation starts.
FIFO operation can be simulated dynamically while simulation is run.		 ash_riple 4477d 17h /bustap-jtag
8 Added fault handling of wrong input length in the GUI. ash_riple 4481d 17h /bustap-jtag
7 Added references related to "Bus Monitor". ash_riple 4481d 21h /bustap-jtag
6 Updated to 2.1. New features added as in doc/Revision History.txt. ash_riple 4482d 17h /bustap-jtag
5 Created code base for 2.x development.
Now supporting pipelined read/write access. Provided wrapper can be used as an example to connect up_monitor to any bus.		 ash_riple 4485d 18h /bustap-jtag

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.