URL https://opencores.org/ocsvn/c16/c16/trunk

Subversion Repositories c16

[/] [c16/] [trunk] - Rev 26

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
26	New directory structure.	root	5568d 04h	/c16/trunk
25	XOR bug fixed	jsauermann	6626d 11h	/trunk
24	no message	jsauermann	6787d 09h	/trunk
23	Fixed problem with wishbone wait-states	jsauermann	6927d 09h	/trunk
21	Changes for Xilinx Proj. Nav. 7.1.02i	jsauermann	6927d 14h	/trunk
19	FPGA Pin desription added.	jsauermann	7123d 11h	/trunk
18	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7424d 10h	/trunk
17	Assert ENABLE_INT and DISABLE_INT only in M1. Thanks to Riccardo Cerulli-Irelly. Requires a fix in rtos.c as well	jsauermann	7424d 10h	/trunk
16	Enable interrupts at start of each task. This fix is required after a change in opcode_decoder.vhd.	jsauermann	7424d 10h	/trunk
15	sample ucf file	jsauermann	7463d 13h	/trunk
14	no message	jsauermann	7471d 14h	/trunk
13	bug in print_unsigned() fixed. Now done as in rtos.c	jsauermann	7514d 07h	/trunk
12	Todo removed	jsauermann	7543d 05h	/trunk
11	First Version	jsauermann	7543d 05h	/trunk
10	Set top of stack of idle task to end of internal memory rather than end of external memory (causing incorrect display of 100 % CPU load).	jsauermann	7543d 07h	/trunk
9	Made cpu_engine WISHBONE compliant. (Somebody please validate it).	jsauermann	7543d 07h	/trunk
8	Initialization of compound auto variables added (was TODO)	jsauermann	7550d 10h	/trunk
7	Handle auto variable declarations in compound statements properly	jsauermann	7551d 09h	/trunk
6	New Target polled for testing compiler without the need to simulate interrupts	jsauermann	7551d 09h	/trunk
5	Initial version	jsauermann	7552d 07h	/trunk

1 2 Next >

Show All

Browse

Tools

Subversion Repositories c16

[/] [c16/] [trunk] - Rev 26

Filtering Options