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[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog] - Rev 104

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Rev	Log message	Author	Age	Path
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7677d 20h	/can/tags/asyst_3/rtl/verilog
102	Little fixes (to fix warnings).	mohor	7680d 10h	/can/tags/asyst_3/rtl/verilog
100	Synchronization changed.	mohor	7684d 12h	/can/tags/asyst_3/rtl/verilog
99	PCI_BIST replaced with CAN_BIST.	mohor	7684d 12h	/can/tags/asyst_3/rtl/verilog
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7689d 23h	/can/tags/asyst_3/rtl/verilog
95	Virtual silicon ram instances added.	simons	7690d 01h	/can/tags/asyst_3/rtl/verilog
93	synthesis full_case parallel_case fixed.	mohor	7695d 12h	/can/tags/asyst_3/rtl/verilog
92	clkout is clk/2 after the reset.	mohor	7695d 20h	/can/tags/asyst_3/rtl/verilog
90	paralel_case and full_case compiler directives added to case statements.	mohor	7696d 09h	/can/tags/asyst_3/rtl/verilog
88	Previous change removed. When resynchronization occurs we go to seg1 stage. sync stage does not cause another start of seg1 stage.	mohor	7697d 07h	/can/tags/asyst_3/rtl/verilog
87	When hard_sync or resync occure we need to go to seg1 segment. Going to sync segment is in that case blocked.	mohor	7697d 07h	/can/tags/asyst_3/rtl/verilog
85	Typo fixed.	mohor	7698d 23h	/can/tags/asyst_3/rtl/verilog
84	clk_cnt reduced from [8:0] to [6:0].	mohor	7700d 06h	/can/tags/asyst_3/rtl/verilog
82	Removed few signals.	mohor	7700d 07h	/can/tags/asyst_3/rtl/verilog
81	"chip select" signal cs_can_i is used only when not using WISHBONE interface.	mohor	7700d 07h	/can/tags/asyst_3/rtl/verilog
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7700d 07h	/can/tags/asyst_3/rtl/verilog
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7701d 07h	/can/tags/asyst_3/rtl/verilog
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7701d 08h	/can/tags/asyst_3/rtl/verilog
77	Synchronization is also needed when transmitting a message.	mohor	7704d 07h	/can/tags/asyst_3/rtl/verilog
76	Counters width changed.	mohor	7704d 07h	/can/tags/asyst_3/rtl/verilog

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[/] [can/] [tags/] [asyst_3/] [rtl/] [verilog] - Rev 104

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