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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5638d 06h	/can/tags/rel_11/rtl/verilog/can_fifo.v
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7708d 00h	/can/tags/rel_11/rtl/verilog/can_fifo.v
99	PCI_BIST replaced with CAN_BIST.	mohor	7714d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7720d 03h	/can/tags/rel_11/rtl/verilog/can_fifo.v
95	Virtual silicon ram instances added.	simons	7720d 05h	/can/tags/rel_11/rtl/verilog/can_fifo.v
85	Typo fixed.	mohor	7729d 03h	/can/tags/rel_11/rtl/verilog/can_fifo.v
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7736d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v
51	Xilinx RAM added.	mohor	7834d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v
48	Actel APA ram supported.	mohor	7838d 03h	/can/tags/rel_11/rtl/verilog/can_fifo.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7848d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v
35	Several registers added. Not finished, yet.	mohor	7853d 05h	/can/tags/rel_11/rtl/verilog/can_fifo.v
31	Wishbone interface added.	mohor	7857d 01h	/can/tags/rel_11/rtl/verilog/can_fifo.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7858d 23h	/can/tags/rel_11/rtl/verilog/can_fifo.v
24	backup.	mohor	7868d 00h	/can/tags/rel_11/rtl/verilog/can_fifo.v
23	Fifo corrected to be synthesizable.	mohor	7881d 08h	/can/tags/rel_11/rtl/verilog/can_fifo.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7883d 12h	/can/tags/rel_11/rtl/verilog/can_fifo.v
17	Addresses corrected to decimal values (previously hex).	mohor	7884d 08h	/can/tags/rel_11/rtl/verilog/can_fifo.v
16	rx_fifo is now working.	mohor	7884d 13h	/can/tags/rel_11/rtl/verilog/can_fifo.v
14	rx fifo added. Not 100 % verified, yet.	mohor	7889d 04h	/can/tags/rel_11/rtl/verilog/can_fifo.v
13	Temporary files (backup).	mohor	7889d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

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