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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5702d 06h	/can/tags/rel_11/rtl/verilog/can_fifo.v
105	This commit was manufactured by cvs2svn to create tag 'rel_11'.		7772d 00h	/can/tags/rel_11/rtl/verilog/can_fifo.v
99	PCI_BIST replaced with CAN_BIST.	mohor	7778d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v
97	Overrun fifo implemented with FFs, because it is not possible to create such a memory.	simons	7784d 03h	/can/tags/rel_11/rtl/verilog/can_fifo.v
95	Virtual silicon ram instances added.	simons	7784d 05h	/can/tags/rel_11/rtl/verilog/can_fifo.v
85	Typo fixed.	mohor	7793d 03h	/can/tags/rel_11/rtl/verilog/can_fifo.v
73	overrun and length_info fifos are initialized at the end of reset.	mohor	7800d 16h	/can/tags/rel_11/rtl/verilog/can_fifo.v
51	Xilinx RAM added.	mohor	7898d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v
48	Actel APA ram supported.	mohor	7902d 03h	/can/tags/rel_11/rtl/verilog/can_fifo.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7912d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v
35	Several registers added. Not finished, yet.	mohor	7917d 05h	/can/tags/rel_11/rtl/verilog/can_fifo.v
31	Wishbone interface added.	mohor	7921d 01h	/can/tags/rel_11/rtl/verilog/can_fifo.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7922d 23h	/can/tags/rel_11/rtl/verilog/can_fifo.v
24	backup.	mohor	7932d 00h	/can/tags/rel_11/rtl/verilog/can_fifo.v
23	Fifo corrected to be synthesizable.	mohor	7945d 08h	/can/tags/rel_11/rtl/verilog/can_fifo.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7947d 12h	/can/tags/rel_11/rtl/verilog/can_fifo.v
17	Addresses corrected to decimal values (previously hex).	mohor	7948d 08h	/can/tags/rel_11/rtl/verilog/can_fifo.v
16	rx_fifo is now working.	mohor	7948d 13h	/can/tags/rel_11/rtl/verilog/can_fifo.v
14	rx fifo added. Not 100 % verified, yet.	mohor	7953d 04h	/can/tags/rel_11/rtl/verilog/can_fifo.v
13	Temporary files (backup).	mohor	7953d 11h	/can/tags/rel_11/rtl/verilog/can_fifo.v

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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_fifo.v] - Rev 161

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