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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5608d 02h	/can/tags/rel_22/rtl/verilog/can_bsp.v
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7204d 15h	/can/tags/rel_22/rtl/verilog/can_bsp.v
145	Arbitration bug fixed.	igorm	7204d 15h	/can/tags/rel_22/rtl/verilog/can_bsp.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7370d 06h	/can/tags/rel_22/rtl/verilog/can_bsp.v
136	Error counters changed.	mohor	7464d 07h	/can/tags/rel_22/rtl/verilog/can_bsp.v
130	mbist signals updated according to newest convention	markom	7578d 16h	/can/tags/rel_22/rtl/verilog/can_bsp.v
129	Error counters changed.	mohor	7595d 00h	/can/tags/rel_22/rtl/verilog/can_bsp.v
126	Error counters fixed to be compatible with Bosch VHDL reference model. Small synchronization changes.	mohor	7595d 21h	/can/tags/rel_22/rtl/verilog/can_bsp.v
125	Synchronization changed, error counters fixed.	mohor	7600d 03h	/can/tags/rel_22/rtl/verilog/can_bsp.v
121	When detecting bus-free, signal bus_free_cnt_en was cleared to zero although the last sampled bit was zero instead of one.	mohor	7627d 15h	/can/tags/rel_22/rtl/verilog/can_bsp.v
112	Tx and rx length are limited to 8 bytes regardless to the DLC value.	tadejm	7669d 06h	/can/tags/rel_22/rtl/verilog/can_bsp.v
110	Fixed according to the linter.	mohor	7671d 06h	/can/tags/rel_22/rtl/verilog/can_bsp.v
107	Fixed according to the linter.	mohor	7671d 08h	/can/tags/rel_22/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7677d 20h	/can/tags/rel_22/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	7680d 10h	/can/tags/rel_22/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7684d 12h	/can/tags/rel_22/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7690d 01h	/can/tags/rel_22/rtl/verilog/can_bsp.v
93	synthesis full_case parallel_case fixed.	mohor	7695d 12h	/can/tags/rel_22/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7696d 09h	/can/tags/rel_22/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7700d 07h	/can/tags/rel_22/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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