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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 107

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Rev	Log message	Author	Age	Path
107	Fixed according to the linter.	mohor	7671d 06h	/can/tags/rel_22/rtl/verilog/can_bsp.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7677d 17h	/can/tags/rel_22/rtl/verilog/can_bsp.v
102	Little fixes (to fix warnings).	mohor	7680d 08h	/can/tags/rel_22/rtl/verilog/can_bsp.v
100	Synchronization changed.	mohor	7684d 10h	/can/tags/rel_22/rtl/verilog/can_bsp.v
95	Virtual silicon ram instances added.	simons	7689d 22h	/can/tags/rel_22/rtl/verilog/can_bsp.v
93	synthesis full_case parallel_case fixed.	mohor	7695d 10h	/can/tags/rel_22/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7696d 07h	/can/tags/rel_22/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7700d 05h	/can/tags/rel_22/rtl/verilog/can_bsp.v
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7701d 05h	/can/tags/rel_22/rtl/verilog/can_bsp.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7701d 05h	/can/tags/rel_22/rtl/verilog/can_bsp.v
75	When switching to tx, sync stage is overjumped.	mohor	7706d 05h	/can/tags/rel_22/rtl/verilog/can_bsp.v
48	Actel APA ram supported.	mohor	7807d 20h	/can/tags/rel_22/rtl/verilog/can_bsp.v
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7817d 19h	/can/tags/rel_22/rtl/verilog/can_bsp.v
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7817d 20h	/can/tags/rel_22/rtl/verilog/can_bsp.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7818d 05h	/can/tags/rel_22/rtl/verilog/can_bsp.v
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7819d 19h	/can/tags/rel_22/rtl/verilog/can_bsp.v
35	Several registers added. Not finished, yet.	mohor	7822d 23h	/can/tags/rel_22/rtl/verilog/can_bsp.v
32	abort_tx added. Bit destuff fixed.	mohor	7825d 05h	/can/tags/rel_22/rtl/verilog/can_bsp.v
31	Wishbone interface added.	mohor	7826d 18h	/can/tags/rel_22/rtl/verilog/can_bsp.v
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7827d 03h	/can/tags/rel_22/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 107

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