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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 136

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Rev Log message Author Age Path
136 Error counters changed. mohor 7527d 06h /can/tags/rel_22/rtl/verilog/can_bsp.v
130 mbist signals updated according to newest convention markom 7641d 14h /can/tags/rel_22/rtl/verilog/can_bsp.v
129 Error counters changed. mohor 7657d 23h /can/tags/rel_22/rtl/verilog/can_bsp.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7658d 19h /can/tags/rel_22/rtl/verilog/can_bsp.v
125 Synchronization changed, error counters fixed. mohor 7663d 01h /can/tags/rel_22/rtl/verilog/can_bsp.v
121 When detecting bus-free, signal bus_free_cnt_en was cleared to zero
although the last sampled bit was zero instead of one.		 mohor 7690d 13h /can/tags/rel_22/rtl/verilog/can_bsp.v
112 Tx and rx length are limited to 8 bytes regardless to the DLC value. tadejm 7732d 05h /can/tags/rel_22/rtl/verilog/can_bsp.v
110 Fixed according to the linter. mohor 7734d 05h /can/tags/rel_22/rtl/verilog/can_bsp.v
107 Fixed according to the linter. mohor 7734d 07h /can/tags/rel_22/rtl/verilog/can_bsp.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7740d 18h /can/tags/rel_22/rtl/verilog/can_bsp.v
102 Little fixes (to fix warnings). mohor 7743d 09h /can/tags/rel_22/rtl/verilog/can_bsp.v
100 Synchronization changed. mohor 7747d 11h /can/tags/rel_22/rtl/verilog/can_bsp.v
95 Virtual silicon ram instances added. simons 7752d 23h /can/tags/rel_22/rtl/verilog/can_bsp.v
93 synthesis full_case parallel_case fixed. mohor 7758d 10h /can/tags/rel_22/rtl/verilog/can_bsp.v
90 paralel_case and full_case compiler directives added to case statements. mohor 7759d 08h /can/tags/rel_22/rtl/verilog/can_bsp.v
80 Form error was detected when stuff bit occured at the end of crc. mohor 7763d 06h /can/tags/rel_22/rtl/verilog/can_bsp.v
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7764d 06h /can/tags/rel_22/rtl/verilog/can_bsp.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7764d 06h /can/tags/rel_22/rtl/verilog/can_bsp.v
75 When switching to tx, sync stage is overjumped. mohor 7769d 06h /can/tags/rel_22/rtl/verilog/can_bsp.v
48 Actel APA ram supported. mohor 7870d 21h /can/tags/rel_22/rtl/verilog/can_bsp.v

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