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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 93

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Rev	Log message	Author	Age	Path
93	synthesis full_case parallel_case fixed.	mohor	7725d 01h	/can/tags/rel_22/rtl/verilog/can_bsp.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7725d 23h	/can/tags/rel_22/rtl/verilog/can_bsp.v
80	Form error was detected when stuff bit occured at the end of crc.	mohor	7729d 21h	/can/tags/rel_22/rtl/verilog/can_bsp.v
79	Bit stuffing corrected when stuffing comes at the end of the crc.	tadejm	7730d 21h	/can/tags/rel_22/rtl/verilog/can_bsp.v
78	tx_point generated one clk earlier. rx_i registered. Data corrected when using extended mode.	mohor	7730d 21h	/can/tags/rel_22/rtl/verilog/can_bsp.v
75	When switching to tx, sync stage is overjumped.	mohor	7735d 21h	/can/tags/rel_22/rtl/verilog/can_bsp.v
48	Actel APA ram supported.	mohor	7837d 12h	/can/tags/rel_22/rtl/verilog/can_bsp.v
45	When a dominant bit was detected at the third bit of the intermission and node had a message to transmit, bit_stuff error could occur. Fixed.	mohor	7847d 11h	/can/tags/rel_22/rtl/verilog/can_bsp.v
44	When bit error occured while active error flag was transmitted, counter was not incremented.	mohor	7847d 12h	/can/tags/rel_22/rtl/verilog/can_bsp.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7847d 20h	/can/tags/rel_22/rtl/verilog/can_bsp.v
36	Most of the registers added. Registers "arbitration lost capture", "error code capture" + few more still need to be added.	mohor	7849d 11h	/can/tags/rel_22/rtl/verilog/can_bsp.v
35	Several registers added. Not finished, yet.	mohor	7852d 15h	/can/tags/rel_22/rtl/verilog/can_bsp.v
32	abort_tx added. Bit destuff fixed.	mohor	7854d 21h	/can/tags/rel_22/rtl/verilog/can_bsp.v
31	Wishbone interface added.	mohor	7856d 10h	/can/tags/rel_22/rtl/verilog/can_bsp.v
30	CAN is working according to the specification. WB interface and more registers (status, IRQ, ...) needs to be added.	mohor	7856d 19h	/can/tags/rel_22/rtl/verilog/can_bsp.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7857d 16h	/can/tags/rel_22/rtl/verilog/can_bsp.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7858d 09h	/can/tags/rel_22/rtl/verilog/can_bsp.v
26	Backup.	mohor	7862d 18h	/can/tags/rel_22/rtl/verilog/can_bsp.v
25	* empty log message *	mohor	7862d 20h	/can/tags/rel_22/rtl/verilog/can_bsp.v
24	backup.	mohor	7867d 10h	/can/tags/rel_22/rtl/verilog/can_bsp.v

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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_bsp.v] - Rev 93

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