URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_defines.v] - Rev 124

Rev	Log message	Author	Age	Path
124	ALTERA_RAM supported.	mohor	7649d 19h	/can/tags/rel_22/rtl/verilog/can_defines.v
115	Artisan ram instances added.	simons	7671d 16h	/can/tags/rel_22/rtl/verilog/can_defines.v
95	Virtual silicon ram instances added.	simons	7719d 11h	/can/tags/rel_22/rtl/verilog/can_defines.v
71	Ports added for the CAN_BIST.	mohor	7737d 21h	/can/tags/rel_22/rtl/verilog/can_defines.v
64	* empty log message *	mohor	7818d 15h	/can/tags/rel_22/rtl/verilog/can_defines.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7827d 04h	/can/tags/rel_22/rtl/verilog/can_defines.v
51	Xilinx RAM added.	mohor	7833d 17h	/can/tags/rel_22/rtl/verilog/can_defines.v
48	Actel APA ram supported.	mohor	7837d 09h	/can/tags/rel_22/rtl/verilog/can_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7858d 06h	/can/tags/rel_22/rtl/verilog/can_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7902d 08h	/can/tags/rel_22/rtl/verilog/can_defines.v
2	Initial	mohor	7908d 16h	/can/tags/rel_22/rtl/verilog/can_defines.v