URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_defines.v] - Rev 130

Rev	Log message	Author	Age	Path
130	mbist signals updated according to newest convention	markom	7578d 11h	/can/tags/rel_22/rtl/verilog/can_defines.v
124	ALTERA_RAM supported.	mohor	7620d 04h	/can/tags/rel_22/rtl/verilog/can_defines.v
115	Artisan ram instances added.	simons	7642d 01h	/can/tags/rel_22/rtl/verilog/can_defines.v
95	Virtual silicon ram instances added.	simons	7689d 20h	/can/tags/rel_22/rtl/verilog/can_defines.v
71	Ports added for the CAN_BIST.	mohor	7708d 05h	/can/tags/rel_22/rtl/verilog/can_defines.v
64	* empty log message *	mohor	7789d 00h	/can/tags/rel_22/rtl/verilog/can_defines.v
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7797d 13h	/can/tags/rel_22/rtl/verilog/can_defines.v
51	Xilinx RAM added.	mohor	7804d 02h	/can/tags/rel_22/rtl/verilog/can_defines.v
48	Actel APA ram supported.	mohor	7807d 18h	/can/tags/rel_22/rtl/verilog/can_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7828d 14h	/can/tags/rel_22/rtl/verilog/can_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7872d 17h	/can/tags/rel_22/rtl/verilog/can_defines.v
2	Initial	mohor	7879d 00h	/can/tags/rel_22/rtl/verilog/can_defines.v