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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_defines.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5607d 18h /can/tags/rel_22/rtl/verilog/can_defines.v
146 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7204d 07h /can/tags/rel_22/rtl/verilog/can_defines.v
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7369d 22h /can/tags/rel_22/rtl/verilog/can_defines.v
137 Header changed. mohor 7463d 23h /can/tags/rel_22/rtl/verilog/can_defines.v
130 mbist signals updated according to newest convention markom 7578d 08h /can/tags/rel_22/rtl/verilog/can_defines.v
124 ALTERA_RAM supported. mohor 7620d 01h /can/tags/rel_22/rtl/verilog/can_defines.v
115 Artisan ram instances added. simons 7641d 22h /can/tags/rel_22/rtl/verilog/can_defines.v
95 Virtual silicon ram instances added. simons 7689d 17h /can/tags/rel_22/rtl/verilog/can_defines.v
71 Ports added for the CAN_BIST. mohor 7708d 02h /can/tags/rel_22/rtl/verilog/can_defines.v
64 *** empty log message *** mohor 7788d 21h /can/tags/rel_22/rtl/verilog/can_defines.v
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7797d 09h /can/tags/rel_22/rtl/verilog/can_defines.v
51 Xilinx RAM added. mohor 7803d 23h /can/tags/rel_22/rtl/verilog/can_defines.v
48 Actel APA ram supported. mohor 7807d 15h /can/tags/rel_22/rtl/verilog/can_defines.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7828d 11h /can/tags/rel_22/rtl/verilog/can_defines.v
9 Header changed, testbench improved to send a frame (crc still missing). mohor 7872d 14h /can/tags/rel_22/rtl/verilog/can_defines.v
2 Initial mohor 7878d 21h /can/tags/rel_22/rtl/verilog/can_defines.v

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