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[/] [can/] [tags/] [rel_22/] [rtl/] [verilog/] [can_registers.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5607d 23h	/can/tags/rel_22/rtl/verilog/can_registers.v
146	This commit was manufactured by cvs2svn to create tag 'rel_22'.		7204d 12h	/can/tags/rel_22/rtl/verilog/can_registers.v
141	Core improved to pass all tests with the Bosch VHDL Reference system.	igorm	7370d 03h	/can/tags/rel_22/rtl/verilog/can_registers.v
125	Synchronization changed, error counters fixed.	mohor	7600d 00h	/can/tags/rel_22/rtl/verilog/can_registers.v
111	Fixed according to the linter. Case statement for data_out joined.	mohor	7671d 04h	/can/tags/rel_22/rtl/verilog/can_registers.v
104	Synchronization fixed. In some strange cases it didn't work according to the VHDL reference model.	tadejm	7677d 17h	/can/tags/rel_22/rtl/verilog/can_registers.v
102	Little fixes (to fix warnings).	mohor	7680d 08h	/can/tags/rel_22/rtl/verilog/can_registers.v
93	synthesis full_case parallel_case fixed.	mohor	7695d 09h	/can/tags/rel_22/rtl/verilog/can_registers.v
92	clkout is clk/2 after the reset.	mohor	7695d 17h	/can/tags/rel_22/rtl/verilog/can_registers.v
90	paralel_case and full_case compiler directives added to case statements.	mohor	7696d 07h	/can/tags/rel_22/rtl/verilog/can_registers.v
70	data_out is already registered in the can_top.v file.	mohor	7708d 08h	/can/tags/rel_22/rtl/verilog/can_registers.v
69	Some features are supported in extended mode only (listen_only_mode...).	mohor	7763d 03h	/can/tags/rel_22/rtl/verilog/can_registers.v
66	unix.	mohor	7789d 02h	/can/tags/rel_22/rtl/verilog/can_registers.v