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[/] [can/] [tags/] [rel_23/] [bench/] [verilog/] [can_testbench.v] - Rev 52

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Rev	Log message	Author	Age	Path
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7833d 20h	/can/tags/rel_23/bench/verilog/can_testbench.v
50	Top level signal names changed.	mohor	7833d 20h	/can/tags/rel_23/bench/verilog/can_testbench.v
48	Actel APA ram supported.	mohor	7837d 12h	/can/tags/rel_23/bench/verilog/can_testbench.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7847d 21h	/can/tags/rel_23/bench/verilog/can_testbench.v
38	Temporary backup version (still fully operable).	mohor	7849d 11h	/can/tags/rel_23/bench/verilog/can_testbench.v
35	Several registers added. Not finished, yet.	mohor	7852d 15h	/can/tags/rel_23/bench/verilog/can_testbench.v
34	Errors monitoring improved. arbitration_lost improved.	mohor	7854d 21h	/can/tags/rel_23/bench/verilog/can_testbench.v
31	Wishbone interface added.	mohor	7856d 10h	/can/tags/rel_23/bench/verilog/can_testbench.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7857d 17h	/can/tags/rel_23/bench/verilog/can_testbench.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7858d 09h	/can/tags/rel_23/bench/verilog/can_testbench.v
26	Backup.	mohor	7862d 18h	/can/tags/rel_23/bench/verilog/can_testbench.v
25	* empty log message *	mohor	7862d 21h	/can/tags/rel_23/bench/verilog/can_testbench.v
24	backup.	mohor	7867d 10h	/can/tags/rel_23/bench/verilog/can_testbench.v
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7881d 22h	/can/tags/rel_23/bench/verilog/can_testbench.v
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7882d 14h	/can/tags/rel_23/bench/verilog/can_testbench.v
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7882d 21h	/can/tags/rel_23/bench/verilog/can_testbench.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7882d 22h	/can/tags/rel_23/bench/verilog/can_testbench.v
17	Addresses corrected to decimal values (previously hex).	mohor	7883d 18h	/can/tags/rel_23/bench/verilog/can_testbench.v
16	rx_fifo is now working.	mohor	7883d 23h	/can/tags/rel_23/bench/verilog/can_testbench.v
15	Temporary version (backup).	mohor	7887d 17h	/can/tags/rel_23/bench/verilog/can_testbench.v

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[/] [can/] [tags/] [rel_23/] [bench/] [verilog/] [can_testbench.v] - Rev 52

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