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[/] [can/] [tags/] [rel_24/] [bench/] - Rev 161

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Rev	Log message	Author	Age	Path
161	New directory structure.	root	5637d 20h	/can/tags/rel_24/bench
150	This commit was manufactured by cvs2svn to create tag 'rel_24'.		7231d 21h	/can/tags/rel_24/bench
140	I forgot to thange one signal name.	igorm	7454d 22h	/can/tags/rel_24/bench
139	Signal bus_off_on added.	igorm	7454d 22h	/can/tags/rel_24/bench
130	mbist signals updated according to newest convention	markom	7608d 09h	/can/tags/rel_24/bench
127	Fixing the core to be Bosch VHDL Reference compatible.	mohor	7624d 18h	/can/tags/rel_24/bench
119	Artisan RAMs added.	mohor	7666d 05h	/can/tags/rel_24/bench
83	cs_can_i is used only when WISHBONE interface is not used.	mohor	7730d 00h	/can/tags/rel_24/bench
68	CAN inturrupt is active low.	mohor	7813d 04h	/can/tags/rel_24/bench
63	ALE changes on negedge of clk.	mohor	7824d 20h	/can/tags/rel_24/bench
61	Bidirectional port_0_i changed to port_0_io. input cs_can changed to cs_can_i.	mohor	7827d 09h	/can/tags/rel_24/bench
60	rd_i and wr_i are active high signals. If 8051 is connected, these two signals need to be negated one level higher.	mohor	7827d 11h	/can/tags/rel_24/bench
59	8051 interface added (besides WISHBONE interface). Selection is made in can_defines.v file.	mohor	7827d 11h	/can/tags/rel_24/bench
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7834d 00h	/can/tags/rel_24/bench
50	Top level signal names changed.	mohor	7834d 00h	/can/tags/rel_24/bench
48	Actel APA ram supported.	mohor	7837d 16h	/can/tags/rel_24/bench
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7848d 01h	/can/tags/rel_24/bench
38	Temporary backup version (still fully operable).	mohor	7849d 15h	/can/tags/rel_24/bench
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7849d 15h	/can/tags/rel_24/bench
35	Several registers added. Not finished, yet.	mohor	7852d 19h	/can/tags/rel_24/bench

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[/] [can/] [tags/] [rel_24/] [bench/] - Rev 161

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