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[/] [can/] [tags/] [rel_6/] [rtl/] [verilog/] [can_bsp.v] - Rev 29

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Rev Log message Author Age Path
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7828d 03h /can/tags/rel_6/rtl/verilog/can_bsp.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7828d 19h /can/tags/rel_6/rtl/verilog/can_bsp.v
26 Backup. mohor 7833d 04h /can/tags/rel_6/rtl/verilog/can_bsp.v
25 *** empty log message *** mohor 7833d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
24 backup. mohor 7837d 20h /can/tags/rel_6/rtl/verilog/can_bsp.v
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7852d 08h /can/tags/rel_6/rtl/verilog/can_bsp.v
21 Data is stored to fifo at the end of ack stage. mohor 7852d 23h /can/tags/rel_6/rtl/verilog/can_bsp.v
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7853d 00h /can/tags/rel_6/rtl/verilog/can_bsp.v
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7853d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7853d 08h /can/tags/rel_6/rtl/verilog/can_bsp.v
16 rx_fifo is now working. mohor 7854d 09h /can/tags/rel_6/rtl/verilog/can_bsp.v
15 Temporary version (backup). mohor 7858d 03h /can/tags/rel_6/rtl/verilog/can_bsp.v
14 rx fifo added. Not 100 % verified, yet. mohor 7858d 23h /can/tags/rel_6/rtl/verilog/can_bsp.v
13 Temporary files (backup). mohor 7859d 06h /can/tags/rel_6/rtl/verilog/can_bsp.v
12 Temp version. mohor 7860d 08h /can/tags/rel_6/rtl/verilog/can_bsp.v
11 Acceptance filter added. mohor 7860d 19h /can/tags/rel_6/rtl/verilog/can_bsp.v
10 Backup version. mohor 7871d 17h /can/tags/rel_6/rtl/verilog/can_bsp.v
9 Header changed, testbench improved to send a frame (crc still missing). mohor 7872d 21h /can/tags/rel_6/rtl/verilog/can_bsp.v
2 Initial mohor 7879d 05h /can/tags/rel_6/rtl/verilog/can_bsp.v

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