Rev |
Log message |
Author |
Age |
Path |
78 |
tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode. |
mohor |
7730d 23h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
75 |
When switching to tx, sync stage is overjumped. |
mohor |
7735d 23h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
48 |
Actel APA ram supported. |
mohor |
7837d 14h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
45 |
When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed. |
mohor |
7847d 13h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
44 |
When bit error occured while active error flag was transmitted, counter was
not incremented. |
mohor |
7847d 14h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
39 |
CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished. |
mohor |
7847d 23h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
36 |
Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added. |
mohor |
7849d 13h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
35 |
Several registers added. Not finished, yet. |
mohor |
7852d 17h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
32 |
abort_tx added. Bit destuff fixed. |
mohor |
7854d 23h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
31 |
Wishbone interface added. |
mohor |
7856d 12h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
30 |
CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added. |
mohor |
7856d 21h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
29 |
Overload fixed. Hard synchronization also enabled at the last bit of
interframe. |
mohor |
7857d 19h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
28 |
Bosch license warning added. Error counters finished. Overload frames
still need to be fixed. |
mohor |
7858d 11h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
26 |
Backup. |
mohor |
7862d 20h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
25 |
*** empty log message *** |
mohor |
7862d 23h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
24 |
backup. |
mohor |
7867d 12h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
22 |
Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57). |
mohor |
7882d 00h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
21 |
Data is stored to fifo at the end of ack stage. |
mohor |
7882d 15h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
20 |
CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). |
mohor |
7882d 16h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |
19 |
RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. |
mohor |
7882d 23h |
/can/tags/rel_6/rtl/verilog/can_bsp.v |