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[/] [can/] [tags/] [rel_6/] [rtl/] [verilog/] [can_bsp.v] - Rev 79

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79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7701d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.
mohor 7701d 08h /can/tags/rel_6/rtl/verilog/can_bsp.v
75 When switching to tx, sync stage is overjumped. mohor 7706d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
48 Actel APA ram supported. mohor 7807d 23h /can/tags/rel_6/rtl/verilog/can_bsp.v
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.
mohor 7817d 21h /can/tags/rel_6/rtl/verilog/can_bsp.v
44 When bit error occured while active error flag was transmitted, counter was
not incremented.
mohor 7817d 22h /can/tags/rel_6/rtl/verilog/can_bsp.v
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.
mohor 7818d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.
mohor 7819d 21h /can/tags/rel_6/rtl/verilog/can_bsp.v
35 Several registers added. Not finished, yet. mohor 7823d 01h /can/tags/rel_6/rtl/verilog/can_bsp.v
32 abort_tx added. Bit destuff fixed. mohor 7825d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
31 Wishbone interface added. mohor 7826d 21h /can/tags/rel_6/rtl/verilog/can_bsp.v
30 CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added.
mohor 7827d 06h /can/tags/rel_6/rtl/verilog/can_bsp.v
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.
mohor 7828d 03h /can/tags/rel_6/rtl/verilog/can_bsp.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.
mohor 7828d 19h /can/tags/rel_6/rtl/verilog/can_bsp.v
26 Backup. mohor 7833d 04h /can/tags/rel_6/rtl/verilog/can_bsp.v
25 *** empty log message *** mohor 7833d 07h /can/tags/rel_6/rtl/verilog/can_bsp.v
24 backup. mohor 7837d 20h /can/tags/rel_6/rtl/verilog/can_bsp.v
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).
mohor 7852d 08h /can/tags/rel_6/rtl/verilog/can_bsp.v
21 Data is stored to fifo at the end of ack stage. mohor 7853d 00h /can/tags/rel_6/rtl/verilog/can_bsp.v
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7853d 00h /can/tags/rel_6/rtl/verilog/can_bsp.v

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