URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 52

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

From rev	To rev	Max revs

Search for

Rev	Log message	Author	Age	Path
52	tx_o is now tristated signal. tx_oen and tx_o combined together.	mohor	7864d 14h	/can/tags/rel_9/bench/verilog/can_testbench.v
50	Top level signal names changed.	mohor	7864d 14h	/can/tags/rel_9/bench/verilog/can_testbench.v
48	Actel APA ram supported.	mohor	7868d 06h	/can/tags/rel_9/bench/verilog/can_testbench.v
39	CAN core finished. Host interface added. Registers finished. Synchronization to the wishbone finished.	mohor	7878d 15h	/can/tags/rel_9/bench/verilog/can_testbench.v
38	Temporary backup version (still fully operable).	mohor	7880d 05h	/can/tags/rel_9/bench/verilog/can_testbench.v
35	Several registers added. Not finished, yet.	mohor	7883d 09h	/can/tags/rel_9/bench/verilog/can_testbench.v
34	Errors monitoring improved. arbitration_lost improved.	mohor	7885d 15h	/can/tags/rel_9/bench/verilog/can_testbench.v
31	Wishbone interface added.	mohor	7887d 04h	/can/tags/rel_9/bench/verilog/can_testbench.v
29	Overload fixed. Hard synchronization also enabled at the last bit of interframe.	mohor	7888d 11h	/can/tags/rel_9/bench/verilog/can_testbench.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7889d 03h	/can/tags/rel_9/bench/verilog/can_testbench.v
26	Backup.	mohor	7893d 12h	/can/tags/rel_9/bench/verilog/can_testbench.v
25	* empty log message *	mohor	7893d 15h	/can/tags/rel_9/bench/verilog/can_testbench.v
24	backup.	mohor	7898d 04h	/can/tags/rel_9/bench/verilog/can_testbench.v
22	Form error supported. When receiving messages, last bit of the end-of-frame does not generate form error. Receiver goes to the idle mode one bit sooner. (CAN specification ver 2.0, part B, page 57).	mohor	7912d 16h	/can/tags/rel_9/bench/verilog/can_testbench.v
20	CRC checking fixed (when bitstuff occurs at the end of a CRC sequence).	mohor	7913d 08h	/can/tags/rel_9/bench/verilog/can_testbench.v
19	RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received.	mohor	7913d 15h	/can/tags/rel_9/bench/verilog/can_testbench.v
18	When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo.	mohor	7913d 16h	/can/tags/rel_9/bench/verilog/can_testbench.v
17	Addresses corrected to decimal values (previously hex).	mohor	7914d 12h	/can/tags/rel_9/bench/verilog/can_testbench.v
16	rx_fifo is now working.	mohor	7914d 17h	/can/tags/rel_9/bench/verilog/can_testbench.v
15	Temporary version (backup).	mohor	7918d 11h	/can/tags/rel_9/bench/verilog/can_testbench.v

1 2 Next >

Show All

Browse

Tools

Subversion Repositories can

[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench.v] - Rev 52

Filtering Options