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[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench_defines.v] - Rev 161

Rev	Log message	Author	Age	Path
161	New directory structure.	root	5605d 07h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
98	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7687d 04h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7817d 02h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7826d 00h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
16	rx_fifo is now working.	mohor	7851d 14h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
13	Temporary files (backup).	mohor	7856d 12h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
11	Acceptance filter added.	mohor	7858d 00h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
10	Backup version.	mohor	7868d 22h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7870d 02h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
8	Testbench define file added. Clock divider register added.	mohor	7870d 10h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v