URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

[/] [can/] [tags/] [rel_9/] [bench/] [verilog/] [can_testbench_defines.v] - Rev 37

Rev	Log message	Author	Age	Path
37	Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted.	mohor	7817d 01h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
28	Bosch license warning added. Error counters finished. Overload frames still need to be fixed.	mohor	7825d 22h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
16	rx_fifo is now working.	mohor	7851d 13h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
13	Temporary files (backup).	mohor	7856d 10h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
11	Acceptance filter added.	mohor	7857d 23h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
10	Backup version.	mohor	7868d 21h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
9	Header changed, testbench improved to send a frame (crc still missing).	mohor	7870d 01h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v
8	Testbench define file added. Clock divider register added.	mohor	7870d 09h	/can/tags/rel_9/bench/verilog/can_testbench_defines.v