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Rev Log message Author Age Path
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7850d 06h /can/tags/rel_9/bench/verilog
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7850d 13h /can/tags/rel_9/bench/verilog
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7850d 14h /can/tags/rel_9/bench/verilog
17 Addresses corrected to decimal values (previously hex). mohor 7851d 10h /can/tags/rel_9/bench/verilog
16 rx_fifo is now working. mohor 7851d 15h /can/tags/rel_9/bench/verilog
15 Temporary version (backup). mohor 7855d 10h /can/tags/rel_9/bench/verilog
14 rx fifo added. Not 100 % verified, yet. mohor 7856d 05h /can/tags/rel_9/bench/verilog
13 Temporary files (backup). mohor 7856d 13h /can/tags/rel_9/bench/verilog
11 Acceptance filter added. mohor 7858d 01h /can/tags/rel_9/bench/verilog
10 Backup version. mohor 7868d 23h /can/tags/rel_9/bench/verilog
9 Header changed, testbench improved to send a frame (crc still missing). mohor 7870d 03h /can/tags/rel_9/bench/verilog
8 Testbench define file added. Clock divider register added. mohor 7870d 11h /can/tags/rel_9/bench/verilog
7 Tripple sampling supported. mohor 7871d 02h /can/tags/rel_9/bench/verilog
6 Commented lines removed. mohor 7871d 04h /can/tags/rel_9/bench/verilog
5 Synchronization working. mohor 7871d 13h /can/tags/rel_9/bench/verilog
2 Initial mohor 7876d 11h /can/tags/rel_9/bench/verilog

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