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[/] [can/] [tags/] [rel_9/] [bench/] [verilog] - Rev 60

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60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7823d 12h /can/tags/rel_9/bench/verilog
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7823d 12h /can/tags/rel_9/bench/verilog
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7830d 01h /can/tags/rel_9/bench/verilog
50 Top level signal names changed. mohor 7830d 01h /can/tags/rel_9/bench/verilog
48 Actel APA ram supported. mohor 7833d 18h /can/tags/rel_9/bench/verilog
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7844d 02h /can/tags/rel_9/bench/verilog
38 Temporary backup version (still fully operable). mohor 7845d 16h /can/tags/rel_9/bench/verilog
37 Define CAN_CLOCK_DIVIDER_MODE not used any more. Deleted. mohor 7845d 16h /can/tags/rel_9/bench/verilog
35 Several registers added. Not finished, yet. mohor 7848d 20h /can/tags/rel_9/bench/verilog
34 Errors monitoring improved. arbitration_lost improved. mohor 7851d 02h /can/tags/rel_9/bench/verilog
31 Wishbone interface added. mohor 7852d 16h /can/tags/rel_9/bench/verilog
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7853d 22h /can/tags/rel_9/bench/verilog
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7854d 14h /can/tags/rel_9/bench/verilog
26 Backup. mohor 7858d 23h /can/tags/rel_9/bench/verilog
25 *** empty log message *** mohor 7859d 02h /can/tags/rel_9/bench/verilog
24 backup. mohor 7863d 15h /can/tags/rel_9/bench/verilog
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7878d 03h /can/tags/rel_9/bench/verilog
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7878d 19h /can/tags/rel_9/bench/verilog
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7879d 02h /can/tags/rel_9/bench/verilog
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7879d 03h /can/tags/rel_9/bench/verilog

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