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[/] [can/] [tags/] [rel_9/] [rtl] - Rev 60

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60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7794d 18h /can/tags/rel_9/rtl
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7794d 18h /can/tags/rel_9/rtl
58 timescale.v is used for simulation only. mohor 7795d 06h /can/tags/rel_9/rtl
57 Mux used for clkout to avoid "gated clocks warning". mohor 7795d 06h /can/tags/rel_9/rtl
56 Doubled declarations removed. mohor 7796d 05h /can/tags/rel_9/rtl
55 wire declaration added. mohor 7796d 05h /can/tags/rel_9/rtl
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7801d 07h /can/tags/rel_9/rtl
51 Xilinx RAM added. mohor 7801d 08h /can/tags/rel_9/rtl
50 Top level signal names changed. mohor 7801d 08h /can/tags/rel_9/rtl
48 Actel APA ram supported. mohor 7805d 00h /can/tags/rel_9/rtl
47 Data is latched on read. mohor 7805d 00h /can/tags/rel_9/rtl
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7814d 22h /can/tags/rel_9/rtl
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7814d 23h /can/tags/rel_9/rtl
41 Incomplete sensitivity list fixed. mohor 7815d 08h /can/tags/rel_9/rtl
40 Typo fixed. mohor 7815d 08h /can/tags/rel_9/rtl
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7815d 08h /can/tags/rel_9/rtl
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.		 mohor 7816d 23h /can/tags/rel_9/rtl
35 Several registers added. Not finished, yet. mohor 7820d 02h /can/tags/rel_9/rtl
33 abort_tx added. mohor 7822d 08h /can/tags/rel_9/rtl
32 abort_tx added. Bit destuff fixed. mohor 7822d 08h /can/tags/rel_9/rtl

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