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[/] [can/] [tags/] [rel_9] - Rev 61

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61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7858d 13h /can/tags/rel_9
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7858d 15h /can/tags/rel_9
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7858d 15h /can/tags/rel_9
58 timescale.v is used for simulation only. mohor 7859d 03h /can/tags/rel_9
57 Mux used for clkout to avoid "gated clocks warning". mohor 7859d 03h /can/tags/rel_9
56 Doubled declarations removed. mohor 7860d 02h /can/tags/rel_9
55 wire declaration added. mohor 7860d 02h /can/tags/rel_9
53 CAN pins located. mohor 7865d 04h /can/tags/rel_9
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7865d 04h /can/tags/rel_9
51 Xilinx RAM added. mohor 7865d 04h /can/tags/rel_9
50 Top level signal names changed. mohor 7865d 04h /can/tags/rel_9
49 Actel APA ram changed. Now synchronous read is used. mohor 7868d 20h /can/tags/rel_9
48 Actel APA ram supported. mohor 7868d 20h /can/tags/rel_9
47 Data is latched on read. mohor 7868d 20h /can/tags/rel_9
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7878d 19h /can/tags/rel_9
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7878d 20h /can/tags/rel_9
43 Directory keeper. mohor 7879d 02h /can/tags/rel_9
42 Initial version of the project. mohor 7879d 02h /can/tags/rel_9
41 Incomplete sensitivity list fixed. mohor 7879d 04h /can/tags/rel_9
40 Typo fixed. mohor 7879d 04h /can/tags/rel_9

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